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1 Description: Bundle our own copy of asm/msr-index.h
2 As of Linux 4.12, asm/msr-index.h is not a userspace-exported header, per
3 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b72e7464e4cf80117938e6adb8c22fdc1ca46d42
4 So to use this header (which only lists defines for register names rather
5 than exposing any kernel interfaces), we need to bundle our own - which also
6 obviates any need for a configure check.
7 Bug-Ubuntu: https://bugs.launchpad.net/bugs/1710799
8 Author: Steve Langasek <steve.langasek@ubuntu.com>
9 Last-Update: 2017-08-15
11 --- collectd-5.7.1.orig/configure.ac
12 +++ collectd-5.7.1/configure.ac
13 @@ -804,29 +804,6 @@ AC_CACHE_CHECK([whether clock_boottime a
14 [c_cv_have_clock_boottime_monotonic="no"]))
17 -# For the turbostat plugin
18 -have_asm_msrindex_h="no"
19 -AC_CHECK_HEADERS(asm/msr-index.h, [have_asm_msrindex_h="yes"])
20 -
21 -if test "x$have_asm_msrindex_h" = "xyes"
22 -then
23 - AC_CACHE_CHECK([whether asm/msr-index.h has MSR_PKG_C10_RESIDENCY],
24 - [c_cv_have_usable_asm_msrindex_h],
25 - AC_COMPILE_IFELSE([AC_LANG_PROGRAM(
26 -[[[
27 -#include<asm/msr-index.h>
28 -]]],
29 -[[[
30 -int y = MSR_PKG_C10_RESIDENCY;
31 -return(y);
32 -]]]
33 - )],
34 - [c_cv_have_usable_asm_msrindex_h="yes"],
35 - [c_cv_have_usable_asm_msrindex_h="no"],
36 - )
37 - )
38 -fi
39 -
40 have_cpuid_h="no"
41 AC_CHECK_HEADERS(cpuid.h, [have_cpuid_h="yes"])
43 @@ -6016,7 +5993,7 @@ then
44 then
45 plugin_ipvs="yes"
46 fi
47 - if test "x$c_cv_have_usable_asm_msrindex_h" = "xyes" && test "x$have_cpuid_h" = "xyes"
48 + if test "x$have_cpuid_h" = "xyes"
49 then
50 plugin_turbostat="yes"
51 fi
52 --- /dev/null
53 +++ collectd-5.7.1/src/asm/msr-index.h
54 @@ -0,0 +1,714 @@
55 +#ifndef _ASM_X86_MSR_INDEX_H
56 +#define _ASM_X86_MSR_INDEX_H
57 +
58 +/*
59 + * CPU model specific register (MSR) numbers.
60 + *
61 + * Do not add new entries to this file unless the definitions are shared
62 + * between multiple compilation units.
63 + */
64 +
65 +/* x86-64 specific MSRs */
66 +#define MSR_EFER 0xc0000080 /* extended feature register */
67 +#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
68 +#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
69 +#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
70 +#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
71 +#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
72 +#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
73 +#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
74 +#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
75 +
76 +/* EFER bits: */
77 +#define _EFER_SCE 0 /* SYSCALL/SYSRET */
78 +#define _EFER_LME 8 /* Long mode enable */
79 +#define _EFER_LMA 10 /* Long mode active (read-only) */
80 +#define _EFER_NX 11 /* No execute enable */
81 +#define _EFER_SVME 12 /* Enable virtualization */
82 +#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
83 +#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
84 +
85 +#define EFER_SCE (1<<_EFER_SCE)
86 +#define EFER_LME (1<<_EFER_LME)
87 +#define EFER_LMA (1<<_EFER_LMA)
88 +#define EFER_NX (1<<_EFER_NX)
89 +#define EFER_SVME (1<<_EFER_SVME)
90 +#define EFER_LMSLE (1<<_EFER_LMSLE)
91 +#define EFER_FFXSR (1<<_EFER_FFXSR)
92 +
93 +/* Intel MSRs. Some also available on other CPUs */
94 +
95 +#define MSR_PPIN_CTL 0x0000004e
96 +#define MSR_PPIN 0x0000004f
97 +
98 +#define MSR_IA32_PERFCTR0 0x000000c1
99 +#define MSR_IA32_PERFCTR1 0x000000c2
100 +#define MSR_FSB_FREQ 0x000000cd
101 +#define MSR_PLATFORM_INFO 0x000000ce
102 +
103 +#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
104 +#define NHM_C3_AUTO_DEMOTE (1UL << 25)
105 +#define NHM_C1_AUTO_DEMOTE (1UL << 26)
106 +#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
107 +#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
108 +#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
109 +
110 +#define MSR_MTRRcap 0x000000fe
111 +#define MSR_IA32_BBL_CR_CTL 0x00000119
112 +#define MSR_IA32_BBL_CR_CTL3 0x0000011e
113 +
114 +#define MSR_IA32_SYSENTER_CS 0x00000174
115 +#define MSR_IA32_SYSENTER_ESP 0x00000175
116 +#define MSR_IA32_SYSENTER_EIP 0x00000176
117 +
118 +#define MSR_IA32_MCG_CAP 0x00000179
119 +#define MSR_IA32_MCG_STATUS 0x0000017a
120 +#define MSR_IA32_MCG_CTL 0x0000017b
121 +#define MSR_IA32_MCG_EXT_CTL 0x000004d0
122 +
123 +#define MSR_OFFCORE_RSP_0 0x000001a6
124 +#define MSR_OFFCORE_RSP_1 0x000001a7
125 +#define MSR_TURBO_RATIO_LIMIT 0x000001ad
126 +#define MSR_TURBO_RATIO_LIMIT1 0x000001ae
127 +#define MSR_TURBO_RATIO_LIMIT2 0x000001af
128 +
129 +#define MSR_LBR_SELECT 0x000001c8
130 +#define MSR_LBR_TOS 0x000001c9
131 +#define MSR_LBR_NHM_FROM 0x00000680
132 +#define MSR_LBR_NHM_TO 0x000006c0
133 +#define MSR_LBR_CORE_FROM 0x00000040
134 +#define MSR_LBR_CORE_TO 0x00000060
135 +
136 +#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
137 +#define LBR_INFO_MISPRED BIT_ULL(63)
138 +#define LBR_INFO_IN_TX BIT_ULL(62)
139 +#define LBR_INFO_ABORT BIT_ULL(61)
140 +#define LBR_INFO_CYCLES 0xffff
141 +
142 +#define MSR_IA32_PEBS_ENABLE 0x000003f1
143 +#define MSR_IA32_DS_AREA 0x00000600
144 +#define MSR_IA32_PERF_CAPABILITIES 0x00000345
145 +#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
146 +
147 +#define MSR_IA32_RTIT_CTL 0x00000570
148 +#define MSR_IA32_RTIT_STATUS 0x00000571
149 +#define MSR_IA32_RTIT_ADDR0_A 0x00000580
150 +#define MSR_IA32_RTIT_ADDR0_B 0x00000581
151 +#define MSR_IA32_RTIT_ADDR1_A 0x00000582
152 +#define MSR_IA32_RTIT_ADDR1_B 0x00000583
153 +#define MSR_IA32_RTIT_ADDR2_A 0x00000584
154 +#define MSR_IA32_RTIT_ADDR2_B 0x00000585
155 +#define MSR_IA32_RTIT_ADDR3_A 0x00000586
156 +#define MSR_IA32_RTIT_ADDR3_B 0x00000587
157 +#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
158 +#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
159 +#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
160 +
161 +#define MSR_MTRRfix64K_00000 0x00000250
162 +#define MSR_MTRRfix16K_80000 0x00000258
163 +#define MSR_MTRRfix16K_A0000 0x00000259
164 +#define MSR_MTRRfix4K_C0000 0x00000268
165 +#define MSR_MTRRfix4K_C8000 0x00000269
166 +#define MSR_MTRRfix4K_D0000 0x0000026a
167 +#define MSR_MTRRfix4K_D8000 0x0000026b
168 +#define MSR_MTRRfix4K_E0000 0x0000026c
169 +#define MSR_MTRRfix4K_E8000 0x0000026d
170 +#define MSR_MTRRfix4K_F0000 0x0000026e
171 +#define MSR_MTRRfix4K_F8000 0x0000026f
172 +#define MSR_MTRRdefType 0x000002ff
173 +
174 +#define MSR_IA32_CR_PAT 0x00000277
175 +
176 +#define MSR_IA32_DEBUGCTLMSR 0x000001d9
177 +#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
178 +#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
179 +#define MSR_IA32_LASTINTFROMIP 0x000001dd
180 +#define MSR_IA32_LASTINTTOIP 0x000001de
181 +
182 +/* DEBUGCTLMSR bits (others vary by model): */
183 +#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
184 +#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
185 +#define DEBUGCTLMSR_TR (1UL << 6)
186 +#define DEBUGCTLMSR_BTS (1UL << 7)
187 +#define DEBUGCTLMSR_BTINT (1UL << 8)
188 +#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
189 +#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
190 +#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
191 +
192 +#define MSR_PEBS_FRONTEND 0x000003f7
193 +
194 +#define MSR_IA32_POWER_CTL 0x000001fc
195 +
196 +#define MSR_IA32_MC0_CTL 0x00000400
197 +#define MSR_IA32_MC0_STATUS 0x00000401
198 +#define MSR_IA32_MC0_ADDR 0x00000402
199 +#define MSR_IA32_MC0_MISC 0x00000403
200 +
201 +/* C-state Residency Counters */
202 +#define MSR_PKG_C3_RESIDENCY 0x000003f8
203 +#define MSR_PKG_C6_RESIDENCY 0x000003f9
204 +#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
205 +#define MSR_PKG_C7_RESIDENCY 0x000003fa
206 +#define MSR_CORE_C3_RESIDENCY 0x000003fc
207 +#define MSR_CORE_C6_RESIDENCY 0x000003fd
208 +#define MSR_CORE_C7_RESIDENCY 0x000003fe
209 +#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
210 +#define MSR_PKG_C2_RESIDENCY 0x0000060d
211 +#define MSR_PKG_C8_RESIDENCY 0x00000630
212 +#define MSR_PKG_C9_RESIDENCY 0x00000631
213 +#define MSR_PKG_C10_RESIDENCY 0x00000632
214 +
215 +/* Interrupt Response Limit */
216 +#define MSR_PKGC3_IRTL 0x0000060a
217 +#define MSR_PKGC6_IRTL 0x0000060b
218 +#define MSR_PKGC7_IRTL 0x0000060c
219 +#define MSR_PKGC8_IRTL 0x00000633
220 +#define MSR_PKGC9_IRTL 0x00000634
221 +#define MSR_PKGC10_IRTL 0x00000635
222 +
223 +/* Run Time Average Power Limiting (RAPL) Interface */
224 +
225 +#define MSR_RAPL_POWER_UNIT 0x00000606
226 +
227 +#define MSR_PKG_POWER_LIMIT 0x00000610
228 +#define MSR_PKG_ENERGY_STATUS 0x00000611
229 +#define MSR_PKG_PERF_STATUS 0x00000613
230 +#define MSR_PKG_POWER_INFO 0x00000614
231 +
232 +#define MSR_DRAM_POWER_LIMIT 0x00000618
233 +#define MSR_DRAM_ENERGY_STATUS 0x00000619
234 +#define MSR_DRAM_PERF_STATUS 0x0000061b
235 +#define MSR_DRAM_POWER_INFO 0x0000061c
236 +
237 +#define MSR_PP0_POWER_LIMIT 0x00000638
238 +#define MSR_PP0_ENERGY_STATUS 0x00000639
239 +#define MSR_PP0_POLICY 0x0000063a
240 +#define MSR_PP0_PERF_STATUS 0x0000063b
241 +
242 +#define MSR_PP1_POWER_LIMIT 0x00000640
243 +#define MSR_PP1_ENERGY_STATUS 0x00000641
244 +#define MSR_PP1_POLICY 0x00000642
245 +
246 +/* Config TDP MSRs */
247 +#define MSR_CONFIG_TDP_NOMINAL 0x00000648
248 +#define MSR_CONFIG_TDP_LEVEL_1 0x00000649
249 +#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
250 +#define MSR_CONFIG_TDP_CONTROL 0x0000064B
251 +#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
252 +
253 +#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
254 +
255 +#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
256 +#define MSR_PKG_ANY_CORE_C0_RES 0x00000659
257 +#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
258 +#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
259 +
260 +#define MSR_CORE_C1_RES 0x00000660
261 +#define MSR_MODULE_C6_RES_MS 0x00000664
262 +
263 +#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
264 +#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
265 +
266 +#define MSR_ATOM_CORE_RATIOS 0x0000066a
267 +#define MSR_ATOM_CORE_VIDS 0x0000066b
268 +#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
269 +#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
270 +
271 +
272 +#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
273 +#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
274 +#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
275 +
276 +/* Hardware P state interface */
277 +#define MSR_PPERF 0x0000064e
278 +#define MSR_PERF_LIMIT_REASONS 0x0000064f
279 +#define MSR_PM_ENABLE 0x00000770
280 +#define MSR_HWP_CAPABILITIES 0x00000771
281 +#define MSR_HWP_REQUEST_PKG 0x00000772
282 +#define MSR_HWP_INTERRUPT 0x00000773
283 +#define MSR_HWP_REQUEST 0x00000774
284 +#define MSR_HWP_STATUS 0x00000777
285 +
286 +/* CPUID.6.EAX */
287 +#define HWP_BASE_BIT (1<<7)
288 +#define HWP_NOTIFICATIONS_BIT (1<<8)
289 +#define HWP_ACTIVITY_WINDOW_BIT (1<<9)
290 +#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
291 +#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
292 +
293 +/* IA32_HWP_CAPABILITIES */
294 +#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
295 +#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
296 +#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
297 +#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
298 +
299 +/* IA32_HWP_REQUEST */
300 +#define HWP_MIN_PERF(x) (x & 0xff)
301 +#define HWP_MAX_PERF(x) ((x & 0xff) << 8)
302 +#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
303 +#define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24)
304 +#define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32)
305 +#define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42)
306 +
307 +/* IA32_HWP_STATUS */
308 +#define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
309 +#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
310 +
311 +/* IA32_HWP_INTERRUPT */
312 +#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
313 +#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
314 +
315 +#define MSR_AMD64_MC0_MASK 0xc0010044
316 +
317 +#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
318 +#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
319 +#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
320 +#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
321 +
322 +#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
323 +
324 +/* These are consecutive and not in the normal 4er MCE bank block */
325 +#define MSR_IA32_MC0_CTL2 0x00000280
326 +#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
327 +
328 +#define MSR_P6_PERFCTR0 0x000000c1
329 +#define MSR_P6_PERFCTR1 0x000000c2
330 +#define MSR_P6_EVNTSEL0 0x00000186
331 +#define MSR_P6_EVNTSEL1 0x00000187
332 +
333 +#define MSR_KNC_PERFCTR0 0x00000020
334 +#define MSR_KNC_PERFCTR1 0x00000021
335 +#define MSR_KNC_EVNTSEL0 0x00000028
336 +#define MSR_KNC_EVNTSEL1 0x00000029
337 +
338 +/* Alternative perfctr range with full access. */
339 +#define MSR_IA32_PMC0 0x000004c1
340 +
341 +/* AMD64 MSRs. Not complete. See the architecture manual for a more
342 + complete list. */
343 +
344 +#define MSR_AMD64_PATCH_LEVEL 0x0000008b
345 +#define MSR_AMD64_TSC_RATIO 0xc0000104
346 +#define MSR_AMD64_NB_CFG 0xc001001f
347 +#define MSR_AMD64_PATCH_LOADER 0xc0010020
348 +#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
349 +#define MSR_AMD64_OSVW_STATUS 0xc0010141
350 +#define MSR_AMD64_LS_CFG 0xc0011020
351 +#define MSR_AMD64_DC_CFG 0xc0011022
352 +#define MSR_AMD64_BU_CFG2 0xc001102a
353 +#define MSR_AMD64_IBSFETCHCTL 0xc0011030
354 +#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
355 +#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
356 +#define MSR_AMD64_IBSFETCH_REG_COUNT 3
357 +#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
358 +#define MSR_AMD64_IBSOPCTL 0xc0011033
359 +#define MSR_AMD64_IBSOPRIP 0xc0011034
360 +#define MSR_AMD64_IBSOPDATA 0xc0011035
361 +#define MSR_AMD64_IBSOPDATA2 0xc0011036
362 +#define MSR_AMD64_IBSOPDATA3 0xc0011037
363 +#define MSR_AMD64_IBSDCLINAD 0xc0011038
364 +#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
365 +#define MSR_AMD64_IBSOP_REG_COUNT 7
366 +#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
367 +#define MSR_AMD64_IBSCTL 0xc001103a
368 +#define MSR_AMD64_IBSBRTARGET 0xc001103b
369 +#define MSR_AMD64_IBSOPDATA4 0xc001103d
370 +#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
371 +
372 +/* Fam 17h MSRs */
373 +#define MSR_F17H_IRPERF 0xc00000e9
374 +
375 +/* Fam 16h MSRs */
376 +#define MSR_F16H_L2I_PERF_CTL 0xc0010230
377 +#define MSR_F16H_L2I_PERF_CTR 0xc0010231
378 +#define MSR_F16H_DR1_ADDR_MASK 0xc0011019
379 +#define MSR_F16H_DR2_ADDR_MASK 0xc001101a
380 +#define MSR_F16H_DR3_ADDR_MASK 0xc001101b
381 +#define MSR_F16H_DR0_ADDR_MASK 0xc0011027
382 +
383 +/* Fam 15h MSRs */
384 +#define MSR_F15H_PERF_CTL 0xc0010200
385 +#define MSR_F15H_PERF_CTR 0xc0010201
386 +#define MSR_F15H_NB_PERF_CTL 0xc0010240
387 +#define MSR_F15H_NB_PERF_CTR 0xc0010241
388 +#define MSR_F15H_PTSC 0xc0010280
389 +#define MSR_F15H_IC_CFG 0xc0011021
390 +
391 +/* Fam 10h MSRs */
392 +#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
393 +#define FAM10H_MMIO_CONF_ENABLE (1<<0)
394 +#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
395 +#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
396 +#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
397 +#define FAM10H_MMIO_CONF_BASE_SHIFT 20
398 +#define MSR_FAM10H_NODE_ID 0xc001100c
399 +
400 +/* K8 MSRs */
401 +#define MSR_K8_TOP_MEM1 0xc001001a
402 +#define MSR_K8_TOP_MEM2 0xc001001d
403 +#define MSR_K8_SYSCFG 0xc0010010
404 +#define MSR_K8_INT_PENDING_MSG 0xc0010055
405 +/* C1E active bits in int pending message */
406 +#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
407 +#define MSR_K8_TSEG_ADDR 0xc0010112
408 +#define MSR_K8_TSEG_MASK 0xc0010113
409 +#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
410 +#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
411 +#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
412 +
413 +/* K7 MSRs */
414 +#define MSR_K7_EVNTSEL0 0xc0010000
415 +#define MSR_K7_PERFCTR0 0xc0010004
416 +#define MSR_K7_EVNTSEL1 0xc0010001
417 +#define MSR_K7_PERFCTR1 0xc0010005
418 +#define MSR_K7_EVNTSEL2 0xc0010002
419 +#define MSR_K7_PERFCTR2 0xc0010006
420 +#define MSR_K7_EVNTSEL3 0xc0010003
421 +#define MSR_K7_PERFCTR3 0xc0010007
422 +#define MSR_K7_CLK_CTL 0xc001001b
423 +#define MSR_K7_HWCR 0xc0010015
424 +#define MSR_K7_FID_VID_CTL 0xc0010041
425 +#define MSR_K7_FID_VID_STATUS 0xc0010042
426 +
427 +/* K6 MSRs */
428 +#define MSR_K6_WHCR 0xc0000082
429 +#define MSR_K6_UWCCR 0xc0000085
430 +#define MSR_K6_EPMR 0xc0000086
431 +#define MSR_K6_PSOR 0xc0000087
432 +#define MSR_K6_PFIR 0xc0000088
433 +
434 +/* Centaur-Hauls/IDT defined MSRs. */
435 +#define MSR_IDT_FCR1 0x00000107
436 +#define MSR_IDT_FCR2 0x00000108
437 +#define MSR_IDT_FCR3 0x00000109
438 +#define MSR_IDT_FCR4 0x0000010a
439 +
440 +#define MSR_IDT_MCR0 0x00000110
441 +#define MSR_IDT_MCR1 0x00000111
442 +#define MSR_IDT_MCR2 0x00000112
443 +#define MSR_IDT_MCR3 0x00000113
444 +#define MSR_IDT_MCR4 0x00000114
445 +#define MSR_IDT_MCR5 0x00000115
446 +#define MSR_IDT_MCR6 0x00000116
447 +#define MSR_IDT_MCR7 0x00000117
448 +#define MSR_IDT_MCR_CTRL 0x00000120
449 +
450 +/* VIA Cyrix defined MSRs*/
451 +#define MSR_VIA_FCR 0x00001107
452 +#define MSR_VIA_LONGHAUL 0x0000110a
453 +#define MSR_VIA_RNG 0x0000110b
454 +#define MSR_VIA_BCR2 0x00001147
455 +
456 +/* Transmeta defined MSRs */
457 +#define MSR_TMTA_LONGRUN_CTRL 0x80868010
458 +#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
459 +#define MSR_TMTA_LRTI_READOUT 0x80868018
460 +#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
461 +
462 +/* Intel defined MSRs. */
463 +#define MSR_IA32_P5_MC_ADDR 0x00000000
464 +#define MSR_IA32_P5_MC_TYPE 0x00000001
465 +#define MSR_IA32_TSC 0x00000010
466 +#define MSR_IA32_PLATFORM_ID 0x00000017
467 +#define MSR_IA32_EBL_CR_POWERON 0x0000002a
468 +#define MSR_EBC_FREQUENCY_ID 0x0000002c
469 +#define MSR_SMI_COUNT 0x00000034
470 +#define MSR_IA32_FEATURE_CONTROL 0x0000003a
471 +#define MSR_IA32_TSC_ADJUST 0x0000003b
472 +#define MSR_IA32_BNDCFGS 0x00000d90
473 +
474 +#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
475 +
476 +#define MSR_IA32_XSS 0x00000da0
477 +
478 +#define FEATURE_CONTROL_LOCKED (1<<0)
479 +#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
480 +#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
481 +#define FEATURE_CONTROL_LMCE (1<<20)
482 +
483 +#define MSR_IA32_APICBASE 0x0000001b
484 +#define MSR_IA32_APICBASE_BSP (1<<8)
485 +#define MSR_IA32_APICBASE_ENABLE (1<<11)
486 +#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
487 +
488 +#define MSR_IA32_TSCDEADLINE 0x000006e0
489 +
490 +#define MSR_IA32_UCODE_WRITE 0x00000079
491 +#define MSR_IA32_UCODE_REV 0x0000008b
492 +
493 +#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
494 +#define MSR_IA32_SMBASE 0x0000009e
495 +
496 +#define MSR_IA32_PERF_STATUS 0x00000198
497 +#define MSR_IA32_PERF_CTL 0x00000199
498 +#define INTEL_PERF_CTL_MASK 0xffff
499 +#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
500 +#define MSR_AMD_PERF_STATUS 0xc0010063
501 +#define MSR_AMD_PERF_CTL 0xc0010062
502 +
503 +#define MSR_IA32_MPERF 0x000000e7
504 +#define MSR_IA32_APERF 0x000000e8
505 +
506 +#define MSR_IA32_THERM_CONTROL 0x0000019a
507 +#define MSR_IA32_THERM_INTERRUPT 0x0000019b
508 +
509 +#define THERM_INT_HIGH_ENABLE (1 << 0)
510 +#define THERM_INT_LOW_ENABLE (1 << 1)
511 +#define THERM_INT_PLN_ENABLE (1 << 24)
512 +
513 +#define MSR_IA32_THERM_STATUS 0x0000019c
514 +
515 +#define THERM_STATUS_PROCHOT (1 << 0)
516 +#define THERM_STATUS_POWER_LIMIT (1 << 10)
517 +
518 +#define MSR_THERM2_CTL 0x0000019d
519 +
520 +#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
521 +
522 +#define MSR_IA32_MISC_ENABLE 0x000001a0
523 +
524 +#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
525 +
526 +#define MSR_MISC_FEATURE_CONTROL 0x000001a4
527 +#define MSR_MISC_PWR_MGMT 0x000001aa
528 +
529 +#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
530 +#define ENERGY_PERF_BIAS_PERFORMANCE 0
531 +#define ENERGY_PERF_BIAS_NORMAL 6
532 +#define ENERGY_PERF_BIAS_POWERSAVE 15
533 +
534 +#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
535 +
536 +#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
537 +#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
538 +
539 +#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
540 +
541 +#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
542 +#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
543 +#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
544 +
545 +/* Thermal Thresholds Support */
546 +#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
547 +#define THERM_SHIFT_THRESHOLD0 8
548 +#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
549 +#define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
550 +#define THERM_SHIFT_THRESHOLD1 16
551 +#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
552 +#define THERM_STATUS_THRESHOLD0 (1 << 6)
553 +#define THERM_LOG_THRESHOLD0 (1 << 7)
554 +#define THERM_STATUS_THRESHOLD1 (1 << 8)
555 +#define THERM_LOG_THRESHOLD1 (1 << 9)
556 +
557 +/* MISC_ENABLE bits: architectural */
558 +#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
559 +#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
560 +#define MSR_IA32_MISC_ENABLE_TCC_BIT 1
561 +#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
562 +#define MSR_IA32_MISC_ENABLE_EMON_BIT 7
563 +#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
564 +#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
565 +#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
566 +#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
567 +#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
568 +#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
569 +#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
570 +#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
571 +#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
572 +#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
573 +#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
574 +#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
575 +#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
576 +#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
577 +#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
578 +
579 +/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
580 +#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
581 +#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
582 +#define MSR_IA32_MISC_ENABLE_TM1_BIT 3
583 +#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
584 +#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
585 +#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
586 +#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
587 +#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
588 +#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
589 +#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
590 +#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
591 +#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
592 +#define MSR_IA32_MISC_ENABLE_FERR_BIT 10
593 +#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
594 +#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
595 +#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
596 +#define MSR_IA32_MISC_ENABLE_TM2_BIT 13
597 +#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
598 +#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
599 +#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
600 +#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
601 +#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
602 +#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
603 +#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
604 +#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
605 +#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
606 +#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
607 +#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
608 +#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
609 +#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
610 +
611 +/* MISC_FEATURE_ENABLES non-architectural features */
612 +#define MSR_MISC_FEATURE_ENABLES 0x00000140
613 +
614 +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT 1
615 +
616 +#define MSR_IA32_TSC_DEADLINE 0x000006E0
617 +
618 +/* P4/Xeon+ specific */
619 +#define MSR_IA32_MCG_EAX 0x00000180
620 +#define MSR_IA32_MCG_EBX 0x00000181
621 +#define MSR_IA32_MCG_ECX 0x00000182
622 +#define MSR_IA32_MCG_EDX 0x00000183
623 +#define MSR_IA32_MCG_ESI 0x00000184
624 +#define MSR_IA32_MCG_EDI 0x00000185
625 +#define MSR_IA32_MCG_EBP 0x00000186
626 +#define MSR_IA32_MCG_ESP 0x00000187
627 +#define MSR_IA32_MCG_EFLAGS 0x00000188
628 +#define MSR_IA32_MCG_EIP 0x00000189
629 +#define MSR_IA32_MCG_RESERVED 0x0000018a
630 +
631 +/* Pentium IV performance counter MSRs */
632 +#define MSR_P4_BPU_PERFCTR0 0x00000300
633 +#define MSR_P4_BPU_PERFCTR1 0x00000301
634 +#define MSR_P4_BPU_PERFCTR2 0x00000302
635 +#define MSR_P4_BPU_PERFCTR3 0x00000303
636 +#define MSR_P4_MS_PERFCTR0 0x00000304
637 +#define MSR_P4_MS_PERFCTR1 0x00000305
638 +#define MSR_P4_MS_PERFCTR2 0x00000306
639 +#define MSR_P4_MS_PERFCTR3 0x00000307
640 +#define MSR_P4_FLAME_PERFCTR0 0x00000308
641 +#define MSR_P4_FLAME_PERFCTR1 0x00000309
642 +#define MSR_P4_FLAME_PERFCTR2 0x0000030a
643 +#define MSR_P4_FLAME_PERFCTR3 0x0000030b
644 +#define MSR_P4_IQ_PERFCTR0 0x0000030c
645 +#define MSR_P4_IQ_PERFCTR1 0x0000030d
646 +#define MSR_P4_IQ_PERFCTR2 0x0000030e
647 +#define MSR_P4_IQ_PERFCTR3 0x0000030f
648 +#define MSR_P4_IQ_PERFCTR4 0x00000310
649 +#define MSR_P4_IQ_PERFCTR5 0x00000311
650 +#define MSR_P4_BPU_CCCR0 0x00000360
651 +#define MSR_P4_BPU_CCCR1 0x00000361
652 +#define MSR_P4_BPU_CCCR2 0x00000362
653 +#define MSR_P4_BPU_CCCR3 0x00000363
654 +#define MSR_P4_MS_CCCR0 0x00000364
655 +#define MSR_P4_MS_CCCR1 0x00000365
656 +#define MSR_P4_MS_CCCR2 0x00000366
657 +#define MSR_P4_MS_CCCR3 0x00000367
658 +#define MSR_P4_FLAME_CCCR0 0x00000368
659 +#define MSR_P4_FLAME_CCCR1 0x00000369
660 +#define MSR_P4_FLAME_CCCR2 0x0000036a
661 +#define MSR_P4_FLAME_CCCR3 0x0000036b
662 +#define MSR_P4_IQ_CCCR0 0x0000036c
663 +#define MSR_P4_IQ_CCCR1 0x0000036d
664 +#define MSR_P4_IQ_CCCR2 0x0000036e
665 +#define MSR_P4_IQ_CCCR3 0x0000036f
666 +#define MSR_P4_IQ_CCCR4 0x00000370
667 +#define MSR_P4_IQ_CCCR5 0x00000371
668 +#define MSR_P4_ALF_ESCR0 0x000003ca
669 +#define MSR_P4_ALF_ESCR1 0x000003cb
670 +#define MSR_P4_BPU_ESCR0 0x000003b2
671 +#define MSR_P4_BPU_ESCR1 0x000003b3
672 +#define MSR_P4_BSU_ESCR0 0x000003a0
673 +#define MSR_P4_BSU_ESCR1 0x000003a1
674 +#define MSR_P4_CRU_ESCR0 0x000003b8
675 +#define MSR_P4_CRU_ESCR1 0x000003b9
676 +#define MSR_P4_CRU_ESCR2 0x000003cc
677 +#define MSR_P4_CRU_ESCR3 0x000003cd
678 +#define MSR_P4_CRU_ESCR4 0x000003e0
679 +#define MSR_P4_CRU_ESCR5 0x000003e1
680 +#define MSR_P4_DAC_ESCR0 0x000003a8
681 +#define MSR_P4_DAC_ESCR1 0x000003a9
682 +#define MSR_P4_FIRM_ESCR0 0x000003a4
683 +#define MSR_P4_FIRM_ESCR1 0x000003a5
684 +#define MSR_P4_FLAME_ESCR0 0x000003a6
685 +#define MSR_P4_FLAME_ESCR1 0x000003a7
686 +#define MSR_P4_FSB_ESCR0 0x000003a2
687 +#define MSR_P4_FSB_ESCR1 0x000003a3
688 +#define MSR_P4_IQ_ESCR0 0x000003ba
689 +#define MSR_P4_IQ_ESCR1 0x000003bb
690 +#define MSR_P4_IS_ESCR0 0x000003b4
691 +#define MSR_P4_IS_ESCR1 0x000003b5
692 +#define MSR_P4_ITLB_ESCR0 0x000003b6
693 +#define MSR_P4_ITLB_ESCR1 0x000003b7
694 +#define MSR_P4_IX_ESCR0 0x000003c8
695 +#define MSR_P4_IX_ESCR1 0x000003c9
696 +#define MSR_P4_MOB_ESCR0 0x000003aa
697 +#define MSR_P4_MOB_ESCR1 0x000003ab
698 +#define MSR_P4_MS_ESCR0 0x000003c0
699 +#define MSR_P4_MS_ESCR1 0x000003c1
700 +#define MSR_P4_PMH_ESCR0 0x000003ac
701 +#define MSR_P4_PMH_ESCR1 0x000003ad
702 +#define MSR_P4_RAT_ESCR0 0x000003bc
703 +#define MSR_P4_RAT_ESCR1 0x000003bd
704 +#define MSR_P4_SAAT_ESCR0 0x000003ae
705 +#define MSR_P4_SAAT_ESCR1 0x000003af
706 +#define MSR_P4_SSU_ESCR0 0x000003be
707 +#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
708 +
709 +#define MSR_P4_TBPU_ESCR0 0x000003c2
710 +#define MSR_P4_TBPU_ESCR1 0x000003c3
711 +#define MSR_P4_TC_ESCR0 0x000003c4
712 +#define MSR_P4_TC_ESCR1 0x000003c5
713 +#define MSR_P4_U2L_ESCR0 0x000003b0
714 +#define MSR_P4_U2L_ESCR1 0x000003b1
715 +
716 +#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
717 +
718 +/* Intel Core-based CPU performance counters */
719 +#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
720 +#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
721 +#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
722 +#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
723 +#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
724 +#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
725 +#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
726 +
727 +/* Geode defined MSRs */
728 +#define MSR_GEODE_BUSCONT_CONF0 0x00001900
729 +
730 +/* Intel VT MSRs */
731 +#define MSR_IA32_VMX_BASIC 0x00000480
732 +#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
733 +#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
734 +#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
735 +#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
736 +#define MSR_IA32_VMX_MISC 0x00000485
737 +#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
738 +#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
739 +#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
740 +#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
741 +#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
742 +#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
743 +#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
744 +#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
745 +#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
746 +#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
747 +#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
748 +#define MSR_IA32_VMX_VMFUNC 0x00000491
749 +
750 +/* VMX_BASIC bits and bitmasks */
751 +#define VMX_BASIC_VMCS_SIZE_SHIFT 32
752 +#define VMX_BASIC_TRUE_CTLS (1ULL << 55)
753 +#define VMX_BASIC_64 0x0001000000000000LLU
754 +#define VMX_BASIC_MEM_TYPE_SHIFT 50
755 +#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
756 +#define VMX_BASIC_MEM_TYPE_WB 6LLU
757 +#define VMX_BASIC_INOUT 0x0040000000000000LLU
758 +
759 +/* MSR_IA32_VMX_MISC bits */
760 +#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
761 +#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
762 +/* AMD-V MSRs */
763 +
764 +#define MSR_VM_CR 0xc0010114
765 +#define MSR_VM_IGNNE 0xc0010115
766 +#define MSR_VM_HSAVE_PA 0xc0010117
767 +
768 +#endif /* _ASM_X86_MSR_INDEX_H */