From: Marc Fournier Date: Wed, 23 Aug 2017 15:51:25 +0000 (+0200) Subject: patches: add local-msr-index-h.patch X-Git-Tag: collectd-5.7.2-1~1 X-Git-Url: https://git.tokkee.org/?a=commitdiff_plain;h=26a29f29d3fd6be0a7901a9968587cd0f2418d8d;p=pkg-collectd.git patches: add local-msr-index-h.patch NB: I don't feel this is the correct solution, and definetely needs to get fixed upstream. So this is more of a temporary workaround for the current FTBFS in sid. --- diff --git a/debian/changelog b/debian/changelog index eda67d4..ea62985 100644 --- a/debian/changelog +++ b/debian/changelog @@ -11,6 +11,8 @@ collectd (5.7.2-1) UNRELEASED; urgency=medium - drop mqtt_resource_leak.patch; included upstream. - add libcollectdclient_error_buffer.patch, fixing a build error with GCC 7 (Closes: #871062). Thanks to Steve Langasek and Ruben Kerkhof. + - add local-msr-index-h.patch, bundling a header file removed from 4.12+ + kernels (Closes: #872276). Thanks to Steve Langasek. -- Marc Fournier Wed, 23 Aug 2017 15:58:47 +0200 diff --git a/debian/patches/local-msr-index-h.patch b/debian/patches/local-msr-index-h.patch new file mode 100644 index 0000000..ca82ecc --- /dev/null +++ b/debian/patches/local-msr-index-h.patch @@ -0,0 +1,768 @@ +Description: Bundle our own copy of asm/msr-index.h + As of Linux 4.12, asm/msr-index.h is not a userspace-exported header, per + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b72e7464e4cf80117938e6adb8c22fdc1ca46d42 + So to use this header (which only lists defines for register names rather + than exposing any kernel interfaces), we need to bundle our own - which also + obviates any need for a configure check. +Bug-Ubuntu: https://bugs.launchpad.net/bugs/1710799 +Author: Steve Langasek +Last-Update: 2017-08-15 + +--- collectd-5.7.1.orig/configure.ac ++++ collectd-5.7.1/configure.ac +@@ -804,29 +804,6 @@ AC_CACHE_CHECK([whether clock_boottime a + [c_cv_have_clock_boottime_monotonic="no"])) + + +-# For the turbostat plugin +-have_asm_msrindex_h="no" +-AC_CHECK_HEADERS(asm/msr-index.h, [have_asm_msrindex_h="yes"]) +- +-if test "x$have_asm_msrindex_h" = "xyes" +-then +- AC_CACHE_CHECK([whether asm/msr-index.h has MSR_PKG_C10_RESIDENCY], +- [c_cv_have_usable_asm_msrindex_h], +- AC_COMPILE_IFELSE([AC_LANG_PROGRAM( +-[[[ +-#include +-]]], +-[[[ +-int y = MSR_PKG_C10_RESIDENCY; +-return(y); +-]]] +- )], +- [c_cv_have_usable_asm_msrindex_h="yes"], +- [c_cv_have_usable_asm_msrindex_h="no"], +- ) +- ) +-fi +- + have_cpuid_h="no" + AC_CHECK_HEADERS(cpuid.h, [have_cpuid_h="yes"]) + +@@ -6016,7 +5993,7 @@ then + then + plugin_ipvs="yes" + fi +- if test "x$c_cv_have_usable_asm_msrindex_h" = "xyes" && test "x$have_cpuid_h" = "xyes" ++ if test "x$have_cpuid_h" = "xyes" + then + plugin_turbostat="yes" + fi +--- /dev/null ++++ collectd-5.7.1/src/asm/msr-index.h +@@ -0,0 +1,714 @@ ++#ifndef _ASM_X86_MSR_INDEX_H ++#define _ASM_X86_MSR_INDEX_H ++ ++/* ++ * CPU model specific register (MSR) numbers. ++ * ++ * Do not add new entries to this file unless the definitions are shared ++ * between multiple compilation units. ++ */ ++ ++/* x86-64 specific MSRs */ ++#define MSR_EFER 0xc0000080 /* extended feature register */ ++#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ ++#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ ++#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ ++#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ ++#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ ++#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ ++#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ ++#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ ++ ++/* EFER bits: */ ++#define _EFER_SCE 0 /* SYSCALL/SYSRET */ ++#define _EFER_LME 8 /* Long mode enable */ ++#define _EFER_LMA 10 /* Long mode active (read-only) */ ++#define _EFER_NX 11 /* No execute enable */ ++#define _EFER_SVME 12 /* Enable virtualization */ ++#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ ++#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ ++ ++#define EFER_SCE (1<<_EFER_SCE) ++#define EFER_LME (1<<_EFER_LME) ++#define EFER_LMA (1<<_EFER_LMA) ++#define EFER_NX (1<<_EFER_NX) ++#define EFER_SVME (1<<_EFER_SVME) ++#define EFER_LMSLE (1<<_EFER_LMSLE) ++#define EFER_FFXSR (1<<_EFER_FFXSR) ++ ++/* Intel MSRs. Some also available on other CPUs */ ++ ++#define MSR_PPIN_CTL 0x0000004e ++#define MSR_PPIN 0x0000004f ++ ++#define MSR_IA32_PERFCTR0 0x000000c1 ++#define MSR_IA32_PERFCTR1 0x000000c2 ++#define MSR_FSB_FREQ 0x000000cd ++#define MSR_PLATFORM_INFO 0x000000ce ++ ++#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 ++#define NHM_C3_AUTO_DEMOTE (1UL << 25) ++#define NHM_C1_AUTO_DEMOTE (1UL << 26) ++#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) ++#define SNB_C1_AUTO_UNDEMOTE (1UL << 27) ++#define SNB_C3_AUTO_UNDEMOTE (1UL << 28) ++ ++#define MSR_MTRRcap 0x000000fe ++#define MSR_IA32_BBL_CR_CTL 0x00000119 ++#define MSR_IA32_BBL_CR_CTL3 0x0000011e ++ ++#define MSR_IA32_SYSENTER_CS 0x00000174 ++#define MSR_IA32_SYSENTER_ESP 0x00000175 ++#define MSR_IA32_SYSENTER_EIP 0x00000176 ++ ++#define MSR_IA32_MCG_CAP 0x00000179 ++#define MSR_IA32_MCG_STATUS 0x0000017a ++#define MSR_IA32_MCG_CTL 0x0000017b ++#define MSR_IA32_MCG_EXT_CTL 0x000004d0 ++ ++#define MSR_OFFCORE_RSP_0 0x000001a6 ++#define MSR_OFFCORE_RSP_1 0x000001a7 ++#define MSR_TURBO_RATIO_LIMIT 0x000001ad ++#define MSR_TURBO_RATIO_LIMIT1 0x000001ae ++#define MSR_TURBO_RATIO_LIMIT2 0x000001af ++ ++#define MSR_LBR_SELECT 0x000001c8 ++#define MSR_LBR_TOS 0x000001c9 ++#define MSR_LBR_NHM_FROM 0x00000680 ++#define MSR_LBR_NHM_TO 0x000006c0 ++#define MSR_LBR_CORE_FROM 0x00000040 ++#define MSR_LBR_CORE_TO 0x00000060 ++ ++#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ ++#define LBR_INFO_MISPRED BIT_ULL(63) ++#define LBR_INFO_IN_TX BIT_ULL(62) ++#define LBR_INFO_ABORT BIT_ULL(61) ++#define LBR_INFO_CYCLES 0xffff ++ ++#define MSR_IA32_PEBS_ENABLE 0x000003f1 ++#define MSR_IA32_DS_AREA 0x00000600 ++#define MSR_IA32_PERF_CAPABILITIES 0x00000345 ++#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 ++ ++#define MSR_IA32_RTIT_CTL 0x00000570 ++#define MSR_IA32_RTIT_STATUS 0x00000571 ++#define MSR_IA32_RTIT_ADDR0_A 0x00000580 ++#define MSR_IA32_RTIT_ADDR0_B 0x00000581 ++#define MSR_IA32_RTIT_ADDR1_A 0x00000582 ++#define MSR_IA32_RTIT_ADDR1_B 0x00000583 ++#define MSR_IA32_RTIT_ADDR2_A 0x00000584 ++#define MSR_IA32_RTIT_ADDR2_B 0x00000585 ++#define MSR_IA32_RTIT_ADDR3_A 0x00000586 ++#define MSR_IA32_RTIT_ADDR3_B 0x00000587 ++#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 ++#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 ++#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 ++ ++#define MSR_MTRRfix64K_00000 0x00000250 ++#define MSR_MTRRfix16K_80000 0x00000258 ++#define MSR_MTRRfix16K_A0000 0x00000259 ++#define MSR_MTRRfix4K_C0000 0x00000268 ++#define MSR_MTRRfix4K_C8000 0x00000269 ++#define MSR_MTRRfix4K_D0000 0x0000026a ++#define MSR_MTRRfix4K_D8000 0x0000026b ++#define MSR_MTRRfix4K_E0000 0x0000026c ++#define MSR_MTRRfix4K_E8000 0x0000026d ++#define MSR_MTRRfix4K_F0000 0x0000026e ++#define MSR_MTRRfix4K_F8000 0x0000026f ++#define MSR_MTRRdefType 0x000002ff ++ ++#define MSR_IA32_CR_PAT 0x00000277 ++ ++#define MSR_IA32_DEBUGCTLMSR 0x000001d9 ++#define MSR_IA32_LASTBRANCHFROMIP 0x000001db ++#define MSR_IA32_LASTBRANCHTOIP 0x000001dc ++#define MSR_IA32_LASTINTFROMIP 0x000001dd ++#define MSR_IA32_LASTINTTOIP 0x000001de ++ ++/* DEBUGCTLMSR bits (others vary by model): */ ++#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ ++#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ ++#define DEBUGCTLMSR_TR (1UL << 6) ++#define DEBUGCTLMSR_BTS (1UL << 7) ++#define DEBUGCTLMSR_BTINT (1UL << 8) ++#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) ++#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) ++#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) ++ ++#define MSR_PEBS_FRONTEND 0x000003f7 ++ ++#define MSR_IA32_POWER_CTL 0x000001fc ++ ++#define MSR_IA32_MC0_CTL 0x00000400 ++#define MSR_IA32_MC0_STATUS 0x00000401 ++#define MSR_IA32_MC0_ADDR 0x00000402 ++#define MSR_IA32_MC0_MISC 0x00000403 ++ ++/* C-state Residency Counters */ ++#define MSR_PKG_C3_RESIDENCY 0x000003f8 ++#define MSR_PKG_C6_RESIDENCY 0x000003f9 ++#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa ++#define MSR_PKG_C7_RESIDENCY 0x000003fa ++#define MSR_CORE_C3_RESIDENCY 0x000003fc ++#define MSR_CORE_C6_RESIDENCY 0x000003fd ++#define MSR_CORE_C7_RESIDENCY 0x000003fe ++#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff ++#define MSR_PKG_C2_RESIDENCY 0x0000060d ++#define MSR_PKG_C8_RESIDENCY 0x00000630 ++#define MSR_PKG_C9_RESIDENCY 0x00000631 ++#define MSR_PKG_C10_RESIDENCY 0x00000632 ++ ++/* Interrupt Response Limit */ ++#define MSR_PKGC3_IRTL 0x0000060a ++#define MSR_PKGC6_IRTL 0x0000060b ++#define MSR_PKGC7_IRTL 0x0000060c ++#define MSR_PKGC8_IRTL 0x00000633 ++#define MSR_PKGC9_IRTL 0x00000634 ++#define MSR_PKGC10_IRTL 0x00000635 ++ ++/* Run Time Average Power Limiting (RAPL) Interface */ ++ ++#define MSR_RAPL_POWER_UNIT 0x00000606 ++ ++#define MSR_PKG_POWER_LIMIT 0x00000610 ++#define MSR_PKG_ENERGY_STATUS 0x00000611 ++#define MSR_PKG_PERF_STATUS 0x00000613 ++#define MSR_PKG_POWER_INFO 0x00000614 ++ ++#define MSR_DRAM_POWER_LIMIT 0x00000618 ++#define MSR_DRAM_ENERGY_STATUS 0x00000619 ++#define MSR_DRAM_PERF_STATUS 0x0000061b ++#define MSR_DRAM_POWER_INFO 0x0000061c ++ ++#define MSR_PP0_POWER_LIMIT 0x00000638 ++#define MSR_PP0_ENERGY_STATUS 0x00000639 ++#define MSR_PP0_POLICY 0x0000063a ++#define MSR_PP0_PERF_STATUS 0x0000063b ++ ++#define MSR_PP1_POWER_LIMIT 0x00000640 ++#define MSR_PP1_ENERGY_STATUS 0x00000641 ++#define MSR_PP1_POLICY 0x00000642 ++ ++/* Config TDP MSRs */ ++#define MSR_CONFIG_TDP_NOMINAL 0x00000648 ++#define MSR_CONFIG_TDP_LEVEL_1 0x00000649 ++#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A ++#define MSR_CONFIG_TDP_CONTROL 0x0000064B ++#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C ++ ++#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D ++ ++#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 ++#define MSR_PKG_ANY_CORE_C0_RES 0x00000659 ++#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A ++#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B ++ ++#define MSR_CORE_C1_RES 0x00000660 ++#define MSR_MODULE_C6_RES_MS 0x00000664 ++ ++#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 ++#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 ++ ++#define MSR_ATOM_CORE_RATIOS 0x0000066a ++#define MSR_ATOM_CORE_VIDS 0x0000066b ++#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c ++#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d ++ ++ ++#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 ++#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 ++#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 ++ ++/* Hardware P state interface */ ++#define MSR_PPERF 0x0000064e ++#define MSR_PERF_LIMIT_REASONS 0x0000064f ++#define MSR_PM_ENABLE 0x00000770 ++#define MSR_HWP_CAPABILITIES 0x00000771 ++#define MSR_HWP_REQUEST_PKG 0x00000772 ++#define MSR_HWP_INTERRUPT 0x00000773 ++#define MSR_HWP_REQUEST 0x00000774 ++#define MSR_HWP_STATUS 0x00000777 ++ ++/* CPUID.6.EAX */ ++#define HWP_BASE_BIT (1<<7) ++#define HWP_NOTIFICATIONS_BIT (1<<8) ++#define HWP_ACTIVITY_WINDOW_BIT (1<<9) ++#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) ++#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) ++ ++/* IA32_HWP_CAPABILITIES */ ++#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) ++#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) ++#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) ++#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) ++ ++/* IA32_HWP_REQUEST */ ++#define HWP_MIN_PERF(x) (x & 0xff) ++#define HWP_MAX_PERF(x) ((x & 0xff) << 8) ++#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) ++#define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) ++#define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) ++#define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) ++ ++/* IA32_HWP_STATUS */ ++#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) ++#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) ++ ++/* IA32_HWP_INTERRUPT */ ++#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) ++#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) ++ ++#define MSR_AMD64_MC0_MASK 0xc0010044 ++ ++#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) ++#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) ++#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) ++#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) ++ ++#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) ++ ++/* These are consecutive and not in the normal 4er MCE bank block */ ++#define MSR_IA32_MC0_CTL2 0x00000280 ++#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) ++ ++#define MSR_P6_PERFCTR0 0x000000c1 ++#define MSR_P6_PERFCTR1 0x000000c2 ++#define MSR_P6_EVNTSEL0 0x00000186 ++#define MSR_P6_EVNTSEL1 0x00000187 ++ ++#define MSR_KNC_PERFCTR0 0x00000020 ++#define MSR_KNC_PERFCTR1 0x00000021 ++#define MSR_KNC_EVNTSEL0 0x00000028 ++#define MSR_KNC_EVNTSEL1 0x00000029 ++ ++/* Alternative perfctr range with full access. */ ++#define MSR_IA32_PMC0 0x000004c1 ++ ++/* AMD64 MSRs. Not complete. See the architecture manual for a more ++ complete list. */ ++ ++#define MSR_AMD64_PATCH_LEVEL 0x0000008b ++#define MSR_AMD64_TSC_RATIO 0xc0000104 ++#define MSR_AMD64_NB_CFG 0xc001001f ++#define MSR_AMD64_PATCH_LOADER 0xc0010020 ++#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 ++#define MSR_AMD64_OSVW_STATUS 0xc0010141 ++#define MSR_AMD64_LS_CFG 0xc0011020 ++#define MSR_AMD64_DC_CFG 0xc0011022 ++#define MSR_AMD64_BU_CFG2 0xc001102a ++#define MSR_AMD64_IBSFETCHCTL 0xc0011030 ++#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 ++#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 ++#define MSR_AMD64_IBSFETCH_REG_COUNT 3 ++#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<