summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 78b1a7a)
raw | patch | inline | side by side (parent: 78b1a7a)
author | Vincent Brillault <git@lerya.net> | |
Sat, 20 Sep 2014 07:55:10 +0000 (09:55 +0200) | ||
committer | Vincent Brillault <git@lerya.net> | |
Sat, 28 Feb 2015 06:35:41 +0000 (07:35 +0100) |
src/turbostat.c | patch | blob | history |
diff --git a/src/turbostat.c b/src/turbostat.c
index f7b0b1d9261f97a0cac044342761f7b6a4004471..482ec5e15e904a65880dd2271b91dfeec891ab7c 100644 (file)
--- a/src/turbostat.c
+++ b/src/turbostat.c
*
* This check is valid for both Intel and AMD
*/
+ eax = ebx = ecx = edx = 0;
__get_cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
if (!(edx & (1 << 8))) {
ERROR("No invariant TSC");
*
* This check is valid for both Intel and AMD
*/
+ eax = ebx = ecx = edx = 0;
__get_cpuid(0x6, &eax, &ebx, &ecx, &edx);
do_dts = eax & (1 << 0);
do_ptm = eax & (1 << 6);
}
if (do_rapl) {
- unsigned long msr;
+ unsigned long long msr;
if (get_msr(0, MSR_RAPL_POWER_UNIT, &msr))
return 0;