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raw | patch | inline | side by side (parent: 64d6b50)
raw | patch | inline | side by side (parent: 64d6b50)
author | Vincent Brillault <git@lerya.net> | |
Fri, 22 Aug 2014 22:46:42 +0000 (00:46 +0200) | ||
committer | Vincent Brillault <git@lerya.net> | |
Sat, 28 Feb 2015 06:35:40 +0000 (07:35 +0100) |
We refuse to run if it's not true, so let's just assume it is
src/turbostat.c | patch | blob | history |
diff --git a/src/turbostat.c b/src/turbostat.c
index 46f74a74dd91fe27396fca548362ae97d0e5d1e6..ca8551a999e8a1a5c335e2d0fec8e33127a8ab34 100644 (file)
--- a/src/turbostat.c
+++ b/src/turbostat.c
static unsigned int has_aperf;
static unsigned int has_epb;
static unsigned int genuine_intel;
-static unsigned int has_invariant_tsc;
static unsigned int do_nehalem_platform_info;
static int do_smi;
static unsigned int do_rapl;
* this check is valid for both Intel and AMD
*/
__get_cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
- has_invariant_tsc = edx & (1 << 8);
-
- if (!has_invariant_tsc) {
+ if (!(edx & (1 << 8))) {
ERROR("No invariant TSC");
return -ERR_NO_INVARIANT_TSC;
}
return -ERR_NO_APERF;
}
- do_nehalem_platform_info = genuine_intel && has_invariant_tsc;
+ do_nehalem_platform_info = genuine_intel;
do_nhm_cstates = genuine_intel; /* all Intel w/ non-stop TSC have NHM counters */
do_smi = do_nhm_cstates;
do_snb_cstates = is_snb(family, model);